SH7785 Datasheet, PDF (1370/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
27.2 Input/Output Pins
Table 27.1 shows the pin configuration of the FLCTL.
Table 27.1 Pin Configuration
Pin Name Function
FCE
Chip enable
I/O
Output
FD7 to
Data I/O
I/O
FD0
FCLE
FALE
Command latch Output
enable
Address latch Output
enable
FRE
Read enable Output
FWE
Write enable Output
Corresponding
Flash Memory
Pin
NAND Type Description
CE
Enables flash memory connected to this
LSI.
Multiplexed with SCIF0_CTS/INTD.
I/O7 to I/O0
I/O pins for command, address, and data.
Multiplexed with MODE3/IRL7,
MODE2/IRL6, MODE1/IRL5,
MODE0/IRL4, MODE11/SCIF4_SCK,
MODE10/SCIF4_RXD,
MODE9/SCIF4_TXD, and
MODE8/SCIF3_SCK.
CLE
Command Latch Enable (CLE)
Asserted when a command is output.
Multiplexed with MODE4/SCIF3_TXD.
ALE
Address Latch Enable (ALE)
Asserted when an address is output.
Negated when data is input or output.
Multiplexed with MODE7/SCIF3_RXD.
RE
Read Enable (RE)
Reads data at the falling edge of RE.
Multiplexed with SCIF0_SCK/HSPI_CLK.
WE
Write Enable
Flash memory latches a command,
address, and data at the rising edge of
WE.
Multiplexed with
SCIF0_TXD/HSPI_TX/MODE8.
Rev.1.00 Jan. 10, 2008 Page 1340 of 1658
REJ09B0261-0100