SH7785 Datasheet, PDF (203/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
31
1-Kbyte page
Virtual address
10 9
0
28
VPN
Offset
Physical address
10 9
0
PPN
Offset
31
4-Kbyte page
VPN
12 11
0
28
Offset
PPN
12 11
0
Offset
31
8-Kbyte page
13 12
0
28
VPN
Offset
PPN
13 12
0
Offset
31
64-Kbyte page
16 15
0
VPN
Offset
28
16 15
0
PPN
Offset
31
18 17
0
256-Kbyte page
VPN
Offset
28
18 17
0
PPN
Offset
31
20 19
0
28
20 19
0
1-Mbyte page
VPN
Offset
PPN
Offset
31
22 21
0
28 22 21
0
4-Mbyte page
VPN
Offset
PPN
Offset
31 26 25
0
28 26 25
0
64-Mbyte page
VPN
Offset
PPN
Offset
Figure 7.12 Relationship between Page Size and Address Format (TLB Extended Mode)
7.4.2 Instruction TLB (ITLB) Configuration
Figure 7.13 shows the configuration of the ITLB in TLB extended mode.
Entry 0
Entry 1
Entry 2
Entry 3
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
PPN[28:10] ESZ[3:0] SH C EPR[5] EPR[3] EPR[2] EPR[0]
PPN[28:10] ESZ[3:0] SH C EPR[5] EPR[3] EPR[2] EPR[0]
PPN[28:10] ESZ[3:0] SH C EPR[5] EPR[3] EPR[2] EPR[0]
PPN[28:10] ESZ[3:0] SH C EPR[5] EPR[3] EPR[2] EPR[0]
Note: Bits EPR[4], EPR[1], D, and WT are not supported.
Figure 7.13 ITLB Configuration (TLB Extended Mode)
Rev.1.00 Jan. 10, 2008 Page 173 of 1658
REJ09B0261-0100