SH7785 Datasheet, PDF (1399/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
(1) Physical Sector
Figure 27.9 shows the relationship between the physical sector address and flash memory address
of NAND-type flash memory.
• For NAND-type flash memory (512 + 16 bytes)
Physical sector address
Bit 17
Bit 0
Physical sector address bits (FLADR[17:0])
Bit 17
Bit 0
Row3
Row2
Row1
Row3
000000
Row2
Order of address output to NAND-type flash memory I/O
Col
Row1
Row2
Row3
Row1
Col
00000000
Col: Column address
Row: Row address
(Page address)
• For NAND-type flash memory (2048 + 64 bytes)
Physical sector address
Bit 17
Bit 0
Physical sector address bits (FLADR[17:0])
Bit 17
Bit 0
Row2
Row1
Col
Note: Since the address at each boundary
(512 + 16 bytes) of a column address is
generated by FLADR[1:0], when using
NAND-type flash memory (2048 + 64 bytes),
set FLADR[1:0] as follows:
00: Address at byte 0
01: Address at (512 + 16)th byte
10: Address at (1024 + 32)th byte
11: Address at (1536 + 48)th byte
Row2
Row1
Col2
00000
0 00
Col1
0000
Order of address output to NAND-type flash memory I/O
Col1
Col2
Row1
Row2
Col: Column address
Row: Row address
(Page address)
Figure 27.9 Example of Sector Number and NAND-Type Flash Memory Address
Expansion
Rev.1.00 Jan. 10, 2008 Page 1369 of 1658
REJ09B0261-0100