SH7785 Datasheet, PDF (569/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
Valid
MA[10]
Valid
MBA[2:0] Valid
High level
Invalid
Invalid
Invalid
Valid Invalid Valid
Invalid Valid Invalid Valid
Valid Invalid Valid Invalid Valid
Example of CL = 3
MDQS[3:0]
tWR
= 3 cycles
MDM[3:0]
Invalid
Invalid
MDQ[31:0]
Invalid
SDRAM WRITE
command bank A
Write data
PRE
bank A
Figure 12.16 tWR
Invalid
ACT
bank A
WRITE
bank A
Figure 12.16 shows a case in which, after a write request, access occurs requiring that bank B be
closed. After the issue of a WRITE command, it is necessary to wait for time tWR or longer after
output of the write data before issuing a PRE command.
Rev.1.00 Jan. 10, 2008 Page 539 of 1658
REJ09B0261-0100