SH7785 Datasheet, PDF (594/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(3) PCI Command Register (PCICMD)
PCICMD controls the basic functions of the PCIC to generate and respond to PCI cycles. When 0
is written to this register, this register ignores access commands from the external PCI device,
other than configuration access.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ FBBE SERRE WCC PER VGAPS MWIE SC BM MS IOS
Initial value: 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
SH R/W: R R R R R R R R/W R/W R/W R R R R/W R/W R/W
PCI R/W: R R R R R R R R/W R/W R/W R R R R/W R/W R/W
Bit
Bit Name
15 to 10 ⎯
9
FBBE
8
SERRE
7
WCC
Initial
Value
All 0
0
0
1
R/W
Description
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
SH: R
PCI: R
PCI Fast Back-to-Back Enable
Specifies whether fast back-to-back control is
performed on the different devices or not when the
PCIC is a master.
0: Enables fast back-to-back control for the same target
1: Enables fast back-to-back control for different targets
(not supported)
SH: R/W SERR Output Control
PCI: R/W Controls the SERR output.
0: SERR output disabled (pulled up by high impedance
and a pull-up resistor)
1: SERR output enabled (SERR = low output)
SH: R/W Wait Cycle Control
PCI: R/W Controls the address/data stepping.
When WCC is 1, both an address and data, only an
address, and only data are output at master write,
master read, and target read respectively for two clock
cycles.
0: Address/data stepping control disabled
1: Address/data stepping control enabled
Rev.1.00 Jan. 10, 2008 Page 564 of 1658
REJ09B0261-0100