SH7785 Datasheet, PDF (699/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Channel Name
Abbrev.
0
DMA source address register B0 SARB0
DMA destination address register B0 DARB0
DMA transfer count register B0
TCRB0
1
DMA source address register B1 SARB1
DMA destination address register B1 DARB1
DMA transfer count register B1
TCRB1
2
DMA source address register B2 SARB2
DMA destination address register B2 DARB2
DMA transfer count register B2
TCRB2
3
DMA source address register B3 SARB3
DMA destination address register B3 DARB3
DMA transfer count register B3
TCRB3
0, 1
DMA extended resource selector 0 DMARS0
2, 3
DMA extended resource selector 1 DMARS1
4, 5
DMA extended resource selector 2 DMARS2
6
DMA source address register 6
SAR6
DMA destination address register 6 DAR6
DMA transfer count register 6
DMA channel control register 6
TCR6
CHCR6
7
DMA source address register 7
SAR7
DMA destination address register 7 DAR7
DMA transfer count register 7
TCR7
DMA channel control register 7
CHCR7
8
DMA source address register 8
SAR8
DMA destination address register 8 DAR8
DMA transfer count register 8
TCR8
DMA channel control register 8
CHCR8
9
DMA source address register 9
SAR9
DMA destination address register 9 DAR9
DMA transfer count register 9
TCR9
DMA channel control register 9
CHCR9
R/W P4 Address
R/W H'FC80 8120
R/W H'FC80 8124
R/W H'FC80 8128
R/W H'FC80 8130
R/W H'FC80 8134
R/W H'FC80 8138
R/W H'FC80 8140
R/W H'FC80 8144
R/W H'FC80 8148
R/W H'FC80 8150
R/W H'FC80 8154
R/W H'FC80 8158
R/W H'FC80 9000
R/W H'FC80 9004
R/W H'FC80 9008
R/W H'FCC0 8020
R/W H'FCC0 8024
R/W H'FCC0 8028
R/W*1 H'FCC0 802C
R/W H'FCC0 8030
R/W H'FCC0 8034
R/W H'FCC0 8038
R/W*1 H'FCC0 803C
R/W H'FCC0 8040
R/W H'FCC0 8044
R/W H'FCC0 8048
R/W*1 H'FCC0 804C
R/W H'FCC0 8050
R/W H'FCC0 8054
R/W H'FCC0 8058
R/W*1 H'FCC0 805C
Area 7
Address
H'1C80 8120
H'1C80 8124
H'1C80 8128
H'1C80 8130
H'1C80 8134
H'1C80 8138
H'1C80 8140
H'1C80 8144
H'1C80 8148
H'1C80 8150
H'1C80 8154
H'1C80 8158
H'1C80 9000
H'1C80 9004
H'1C80 9008
H'1CC0 8020
H'1CC0 8024
H'1CC0 8028
H'1CC0 802C
H'1CC0 8030
H'1CC0 8034
H'1CC0 8038
H'1CC0 803C
H'1CC0 8040
H'1CC0 8044
H'1CC0 8048
H'1CC0 804C
H'1CC0 8050
H'1CC0 8054
H'1CC0 8058
H'1CC0 805C
Access Sync
Size*³ clock
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
32
Bck
16
Pck
16
Pck
16
Pck
32
Bck
32
Bck
32
Bck
32
Bck,
Pck*4
32
Bck
32
Bck
32
Bck
32
Bck,
Pck*4
32
Bck
32
Bck
32
Bck
32
Bck,
Pck*4
32
Bck
32
Bck
32
Bck
32
Bck,
Pck*4
Rev.1.00 Jan. 10, 2008 Page 669 of 1658
REJ09B0261-0100