SH7785 Datasheet, PDF (1211/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the data transmission should be
temporarily halted by FIFO full/empty, and it should be resumed when the preparation has been
completed.
In multiple block transfer, the transfer should be temporarily halted at every block break to select
either to continue to the next block or to abort the multiple block transfer command by issuing the
CMD12 command. To continue to the next block, the RD_CONTI and DATAEN bits should be
set to 1. To issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command
sequence on the MMCIF side. When using the auto-mode for a pre-defined multiple block
transfer, the setting of the RD_CONTI bit or the DATAEN bit between blocks can be omitted.
24.3.4 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Bit: 7
6
5
4
3
2
1
0
BUSY
FIFO_
FULL
FIFO_
EMPTY
CWRE
DTBUSY
DTBUSY
_TU
—
REQ
Initial value: 0
0
0
0
0
—
0
0
R/W: R
RR
RR
RR
R
Initial
Bit
Bit Name Value R/W Description
7
BUSY
0
R
Command Busy
Indicates command execution status. When the
CMDOFF bit in OPCR is set to 1, this bit is cleared to 0
because the MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
6
FIFO_FULL 0
R
FIFO Full
This bit is set to 1 when the FIFO becomes full while
data is being received from the card, and cleared to 0
when RD_CONTI is set to 1 or the command sequence
is completed.
Indicates whether the FIFO is empty or not.
0: The FIFO is empty.
1: The FIFO is full.
Rev.1.00 Jan. 10, 2008 Page 1181 of 1658
REJ09B0261-0100