SH7785 Datasheet, PDF (245/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Caches
8.2 Register Descriptions
The following registers are related to cache.
Table 8.3 Register Configuration
Register Name
Abbreviation R/W P4 Address*
Area 7 Address* Size
Cache control register
CCR
R/W H'FF00 001C
H'1F00 001C
32
Queue address control register 0 QACR0
R/W H'FF00 0038
H'1F00 0038
32
Queue address control register 1 QACR1
R/W H'FF00 003C
H'1F00 003C
32
On-chip memory control register RAMCR
R/W H'FF00 0074
H'1F00 0074
32
Note: * These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 8.4 Register States in Each Processing State
Register Name
Abbreviation
Cache control register
CCR
Queue address control register 0 QACR0
Queue address control register 1 QACR1
On-chip memory control register RAMCR
Power-on Reset Manual Reset
H'0000 0000 H'0000 0000
Undefined
Undefined
Undefined
Undefined
H'0000 0000 H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Rev.1.00 Jan. 10, 2008 Page 215 of 1658
REJ09B0261-0100