SH7785 Datasheet, PDF (647/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(17) PCI Memory Bank Mask Register 0 (PCIMBMR0)
This register is the mask register for PCIMBR0. This register specifies the memory space size on
the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC.
See section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————
MSBAM0
——
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit
Bit Name
31 to 24 ⎯
Initial
Value
All 0
R/W
SH: R
PCI: ⎯
23 to 18 MSBAM0 000000 SH: R/W
PCI: ⎯
17 to 0 ⎯
All 0 SH: R
PCI: ⎯
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Memory Space 0 Bank Address Mask (6 bits)
0000 00: 256 kbytes
0000 01: 512 kbytes
0000 11: 1 Mbyte
0001 11: 2 Mbytes
0011 11: 4 Mbytes
0111 11: 8 Mbytes
1111 11: 16 Mbytes
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 617 of 1658
REJ09B0261-0100