SH7785 Datasheet, PDF (902/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.17 Equal Pulse Width Register (EQWR)
The equal pulse width register (EQWR) sets the low-level pulse width of a pulse equivalent to the
CSYNC signal. The value is retained during power-on reset and manual reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—————————
EQW
Initial value: 0
0
0
0
0
0
0
0
0 ———————
R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W
Internal update:
OOOOOOO
Bit
31 to 7
6 to 0
Initial
Bit Name Value R/W
⎯
All 0
R
EQW
Undefined R/W
Internal
Update Description
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Yes
Equal Pulse Width
The low-level pulse width of a pulse equivalent
to the CSYNC signal should be set in dot clock
units.
To enable this setting, bit 1 of the CSY bits in
DSMR should be set to 1.
Rev.1.00 Jan. 10, 2008 Page 872 of 1658
REJ09B0261-0100