SH7785 Datasheet, PDF (1359/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

(1) Transmission Using DMA Controller
Start
Release reset,
specify configuration bits
in SSICR
Setup DMA controller to provide data
as required for transmission
Enable SSI module,
enable DMA,
enable error interrupts
Wait for interrupt from DMAC or SSI
26. Serial Sound Interface (SSI) Module
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
SSI
Yes
error interrupt?
No
Has DMAC
Tx data been
completed?
Yes
More data to be send?
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
Wait for idle interrupt
from SSI module
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
End*
Note: * When SSI error interrupt occurs (underflow/overflow), back to start
and execute flow again.
Figure 26.21 Transmission Using DMA Controller
Rev.1.00 Jan. 10, 2008 Page 1329 of 1658
REJ09B0261-0100