SH7785 Datasheet, PDF (793/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.3.1 Watchdog Timer Stop Time Register (WDTST)
WDTST is a 32-bit readable/writable register that specifies the time until watchdog timer counter
WDTCNT overflows. The time until WDTCNT overflows becomes minimum when H'5A00 0001
is set, and maximum when H'5A00 0000 is set.
WDTST should be written as a longword unit, with H'5A in the most significant byte. The value
read from this byte is always H'00. WDTST is only rest by a power-on reset caused by the
PRESET pin.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Code for writing (H'5A)
⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯
WDTST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 24 (Code for All 0 R/W
writing)
23 to 12 ⎯
All 0 R
11 to 0 WDTST All 0 R/W
Description
Code for writing (H'5A)
These bits are always read as H'00. When writing to
this register, the value written to these bits must be
H'5A.
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Stop
These bits set the counter value at which WDTCNT
overflows.
H'001: Minimum overflow value
H'000: Maximum overflow value
Rev.1.00 Jan. 10, 2008 Page 763 of 1658
REJ09B0261-0100