SH7785 Datasheet, PDF (323/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(10) Interrupt Mask Clear Register 2 (INTMSKCLR2)
INTMSKCLR2 is a 32-bit write-only register that clears the mask settings for the IRL interrupt
requests for each input level pattern on the IRL pins. Undefined values are read from this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC015 IC014 IC013 IC012 IC011 IC010 IC009 IC008 IC007 IC006 IC005 IC004 IC003 IC002 IC001 ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IC115 IC114 IC113 IC112 IC111 IC110 IC109 IC108 IC107 IC106 IC105 IC104 IC103 IC102 IC101 ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Name
Value R/W Description
31
IC015
0
30
IC014
0
29
IC013
0
28
IC012
0
R/W Clears masking of the
[When read]
interrupt source of IRL3 to _{Undefined values are}
IRL0 = LLLL (H'0).
read.
R/W Clears masking of the
[When written]
interrupt source of IRL3 to
IRL0 = LLLH (H'1).
0: No effect
1: Clears the
R/W Clears masking of the
corresponding interrupt
interrupt source of IRL3 to
mask (enables the
IRL0 = LLHL (H'2).
interrupt)
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = LLHH (H'3).
27
IC011
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = LHLL (H'4).
26
IC010
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = LHLH (H'5).
25
IC009
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = LHHL (H'6).
24
IC008
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = LHHH (H'7).
Rev.1.00 Jan. 10, 2008 Page 293 of 1658
REJ09B0261-0100