SH7785 Datasheet, PDF (823/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Mode
17.4 Sleep Mode
17.4.1 Transition to Sleep Mode
When the SLEEP instruction is executed, the state is changed from the program execution state to
sleep mode. Although the CPU is stopped after the instruction is executed, the contents of the
CPU register are retained.
On-chip modules other than the CPU continue to operate. The clock is output to the CLKOUT pin.
In sleep mode, a high level signal is output to the STATUS1 pin, and a low level signal is output
to the STATUS0 pin.
Complete the operation of DU before transition to sleep mode. Confirm that the operation of
GDTA is completed. The operation is not guaranteed if transition to sleep mode is performed
while the module is operating.
17.4.2 Releasing Sleep Mode
Sleep mode is released by interrupts (NMI, IRQ/IRL[7:0], and on-chip module) and reset.
In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If needed, put
SPC, SSR, etc to stack before executing the SLEEP instruction.
(1) Release by Interrupts
When the NMI, IRQ/IRL[7:0], and on-chip module interrupts are generated, sleep mode is
released and exception handling of interrupts are performed. The code corresponding to the
interrupt sources is set to the INTEVT register.
For details of the timing of the changes in the STATUS pin, see section 17.7.2, Releasing Sleep
Mode.
(2) Release by a Reset
Sleep mode is released by a power-on reset by the PRESET pin, power-on reset by WDT
overflow, H-UDI reset, and manual reset. For details of the timing of the changes in the STATUS
pin, see section 16.5, Status Pin Change Timing during Reset.
Rev.1.00 Jan. 10, 2008 Page 793 of 1658
REJ09B0261-0100