SH7785 Datasheet, PDF (565/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
MA[10]
MBA[2:0]
Invalid
High level
Invalid
Invalid
Invalid
MDQS[3:0]
MDM[3:0]
MDQ[31:0]
Invalid
Invalid
SDRAM
command
PALL
REF
Figure 12.12 Auto-Refresh Operation
Figure 12.13 shows the self-refresh operation. In order to perform self-refresh operation, the
sequence must be observed. For details, refer to section 12.5.4, Self-Refresh Operation.
When performing processing according to the sequence in section 12.5.4, Self-Refresh Operation,
commands to be issued to the SDRAM are those shown in figure 12.13. Before the transition to
self-refresh, the PALL command is issued in software. Then, software is used to issue the REF
command, and the SLFRSH (self-refresh entry from IDLE) command is issued. The SDRAM
continues in self-refresh mode until self-refresh is cancelled in software. After issuing the
SLFRSHX (self-refresh exit) command in software, it is necessary to wait for the time (tXSNR)
specified in the datasheet for the SDRAM being used until issuing a REF command. A wait
Rev.1.00 Jan. 10, 2008 Page 535 of 1658
REJ09B0261-0100