SH7785 Datasheet, PDF(697/1692 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7785 Datasheet, PDF (697/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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14. Direct Memory Access Controller (DMAC)

14.2 Input/Output Pins

The DMAC-related external pins are shown below.

Table 14.1 shows the configuration of the pins that are connected to external device. The DMAC

has pins for four channels (channels 0 to 3) used in the external bus.

Table 14.1 Pin Configuration for the External Bus

Channel Function

Pin Name I/O Description

0

DMA transfer request DREQ0*1 Input DMA transfer request input from external

device to channel 0

DREQ0 acceptance

confirmation

DRAK0*2

Output Notifies acceptance of DMA transfer

request and start of execution from

channel 0 to external device

DMA transfer end

notification

DACK0*2 Output Outputs strobe to DMA transfer request

from channel 0 to external device

1

DMA transfer request DREQ1*1 Input DMA transfer request input from external

device to channel 1

DREQ1 acceptance

confirmation

DRAK1*2

Output Notifies acceptance of DMA transfer

request and start of execution from

channel 1 to external device

DMA transfer end

notification

DACK1*2 Output Outputs strobe to DMA transfer request

from channel 1 to external device

2

DMA transfer request DREQ2*1 Input DMA transfer request input from external

device to channel 2

DREQ2 acceptance

confirmation

DRAK2*2

Output Notifies acceptance of DMA transfer

request and start of execution from

channel 2 to external device

DMA transfer end

notification

DACK2*2 Output Outputs strobe to DMA transfer request

from channel 2 to external device

3

DMA transfer request DREQ3*1 Input DMA transfer request input from external

device to channel 3

DREQ3 acceptance

confirmation

DRAK3*2

Output Notifies acceptance of DMA transfer

request and start of execution from

channel 3 to external device.

DMA transfer end

notification

DACK3*2 Output Outputs strobe to DMA transfer request

from channel 3 to external device

Notes: 1. The initial value is low-level detection.

2. The initial value is low-active.

Rev.1.00 Jan. 10, 2008 Page 667 of 1658

REJ09B0261-0100

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