SH7785 Datasheet, PDF (1024/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.15 CL Frame Width Setting Register (CLWR)
CLWR is in the CL register block and sets the input image width in pixel units.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯
CL_W
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 12 ⎯
All 0 ⎯
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 CL_W
All 0 R/W Frame width setting
Should be set in pixel units.
Value set should be 2 × n (n: an integer greater than 0)
Notes: 1. CL processing is prohibited when the setting is 0.
2. Addition is performed taking that 1 pixel = 1 byte.
3. CLWR (bytes) + CLIYPR (bytes) should be 32 bytes × n (n: an integer greater than 0)
4. CLWR (bytes)/2 + CLUVPR (bytes) should be 32 bytes × n (n: an integer greater than
0)
Rev.1.00 Jan. 10, 2008 Page 994 of 1658
REJ09B0261-0100