SH7785 Datasheet, PDF (705/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the source address of the next transfer. A word or
longword boundary address should be specified when a word or longword transfer is performed
respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte or 32-byte
transfer is performed respectively.
In 29-bit address mode, the source address is changed as follows before it is output.
• The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used.
• The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used.
• The written address is output as it is when bits 31 to 29 are 111.
In 32-bit address mode, the written address is output as it is.
The initial value of SAR is undefined.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.1.00 Jan. 10, 2008 Page 675 of 1658
REJ09B0261-0100