SH7785 Datasheet, PDF (96/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Pipelining
Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their
descriptions are listed in table 4.1.
Table 4.1 Representations of Instruction Execution Patterns
Representation
E1 E2 E3 WB
S1 S2 S3 WB
s1 s2 s3 WB
E1/S1
, ^{E1S1 E1s1}
M2 M3 MS
FE1 FE2 FE3 FE4 FE5 FE6 FS
FS1 FS2 FS3 FS4 FS
ID
Description
CPU EX pipe is occupied
CPU LS pipe is occupied (with memory access)
CPU LS pipe is occupied (without memory access)
Either CPU EX pipe or CPU LS pipe is occupied
Both CPU EX pipe and CPU LS pipe are occupied
CPU MULT operation unit is occupied
FPU-EX pipe is occupied
FPU-LS pipe is occupied
ID stage is locked
Both CPU and FPU pipes are occupied
Rev.1.00 Jan. 10, 2008 Page 66 of 1658
REJ09B0261-0100