SH7785 Datasheet, PDF (305/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
Table 10.4 Register States in Each Operating Mode
Name
Abbreviation
Interrupt control
register 0
ICR0
Interrupt control
register 1
ICR1
Interrupt priority
register
INTPRI
Interrupt source
register
INTREQ
Interrupt mask
register 0
INTMSK0
Interrupt mask
register 1
INTMSK1
Interrupt mask
register 2
INTMSK2
Interrupt mask clear INTMSKCLR0
register 0
Interrupt mask clear INTMSKCLR1
register 1
Interrupt mask clear INTMSKCLR2
register 2
NMI flag control
register
NMIFCR
User interrupt mask USERIMASK
level register
Interrupt priority
registers
INT2PRI0
INT2PRI1
INT2PRI2
INT2PRI3
INT2PRI4
INT2PRI5
INT2PRI6
Power-on
Manual Reset
Reset by
by
PRESET
WDT/Multiple
Pin/WDT/H-UDI Exception
H'x000 0000* H'x000 0000*
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
H'FF00 0000 H'FF00 0000
H'FF00 0000 H'FF00 0000
H'xx00 0000 H'xx00 0000
H'x000 0000 H'x000 0000
H'xxxx xxxx
H'xxxx xxxx
H'x000 0000* H'x000 0000*
H'0000 0000 H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
Sleep by
SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Deep Sleep by
SLEEP
Instruction
(DSLP = 1)
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev.1.00 Jan. 10, 2008 Page 275 of 1658
REJ09B0261-0100