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SH7785 Datasheet, PDF (33/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Item
FPU
1. Overview
Features
⢠On-chip floating-point coprocessor
⢠Supports single (32-bit) and double (64-bit) precisions
⢠Supports IEEE754-compliant data types and exceptions
⢠Two rounding modes: Round to Nearest and Round to Zero
⢠Handling of denormalized numbers: Truncation to zero or interrupt-
generation for IEEE754 compliance
⢠Floating-point registers: 32 bits à 16 words à 2 banks
(single-precision à 16 words or double-precision à 8 words) à 2 banks
⢠32-bit CPU-FPU floating-point communications register (FPUL)
⢠Supports FMAC (multiply-and-accumulate) instruction
⢠Supports FDIV (divide) and FSQRT (square root) instructions
⢠Supports FLDI0/FLDI1 (load constants 0 and 1) instructions
⢠Instruction-execution times
⯠Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (double-
precision)
⯠Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (double-
precision)
⯠Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision)
⯠Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (double-
precision)
Note: FMAC only supports single-precision operands.
⢠3-D graphics instructions (single-precision only)
⯠4-dimensional vector-conversion and matrix operations (FTRV):
4 cycles (pitch), 8 cycles (latency)
⯠4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles
(latency)
⢠Ten-stage pipeline
Rev.1.00 Jan. 10, 2008 Page 3 of 1658
REJ09B0261-0100
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