SH7785 Datasheet, PDF (286/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. On-Chip Memory
9.3 Operation
9.3.1 Instruction Fetch Access from the CPU
(1) OL Memory
Instruction fetch access from the CPU is performed via the cache/RAM internal bus. This access
takes more than one cycle.
(2) IL Memory
Instruction fetch access from the CPU is performed directly via the instruction bus for a given
virtual address. In the case of successive accesses to the same page of IL memory and as long as
no page conflict occurs, the access takes one cycle.
(3) U Memory
Instruction fetch access from the CPU is performed via the cache/RAM internal bus, and one
instruction fetch takes more than one cycle.
9.3.2 Operand Access from the CPU and Access from the FPU
Note: Operand access is applied for PC relative access (@(disp,pc)).
(1) OL Memory
Access from the CPU or FPU is performed via the operand bus for a given virtual address. Read
access from the operand bus by virtual address takes one cycle if the access is made successively
to the same page of OL memory and as long as no page conflict occurs. Write access from the
operand bus by virtual address takes one cycle as long as no page conflict occurs.
(2) IL Memory
Operand access from the CPU and access from the FPU are performed via the cache/RAM internal
bus. Access via the cache/RAM internal bus takes more than one cycle.
Rev.1.00 Jan. 10, 2008 Page 256 of 1658
REJ09B0261-0100