SH7785 Datasheet, PDF (878/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Initial
Internal
Bit
Bit Name Value R/W Update Description
7, 6
CSY
00
R/W None CSYNC Mode
For details of CSYNC waveform, refer to section
19.5.2, CSYNC.
00: The relation among VSYNC, HSYNC, and
CSYNC is as follows.
VSYNC HSYNC CSYNC
Low level Low level High level
Low level High level Low level
High level Low level Low level
High level High level High level
01: Setting prohibited
10: For the interval of three raster scans after
the falling edge of VSYNC an equivalent
pulse is output, followed by separation pulse
for three raster scans, then an equivalent
pulse for three raster scans, and for the
interval after this the HSYNC waveform is
output as CSYNC.
11: 1/2 raster scan after the VSYNC falling
edge, an equivalent pulse is output for 2.5
raster scans, then separation pulse for 2.5
raster scans, then an equivalent pulse for
2.5 raster scans, and for the interval after
this the HSYNC waveform is output as
CSYNC.
5 to 0 ⎯
All 0
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * The bit is updated by setting the DRES bit in DSYSR to 1.
Rev.1.00 Jan. 10, 2008 Page 848 of 1658
REJ09B0261-0100