SH7785 Datasheet, PDF (578/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
MCKE to high level, upon power-on reset the data within the SDRAM is destroyed. Hence if the
state signal is not set in advance to a state other than power supply backup state, there is the
danger that the destroyed data may be treated as the correct data.)
In this way, procedures are used to make a transition to and cancel SDRAM power supply backup
mode; if these procedures are not followed, the data in the SDRAM may be destroyed.
These procedures are explained below.
(1) Transition to SDRAM Power Supply Backup Mode
The following method is used.
1. Confirm that the controller is not being accessed. The time required for transition must not
exceed the auto-refresh interval requested by the SDRAM by interrupts or some other causes.
2. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 0 (access disabled).
3. Set the ARFEN bit in the SDRAM refresh control register 0 (DBRFCNT0) to 0 (automatic
issue of auto-refresh disabled).
4. Use the CMD bits in the SDRAM command control register (DBCMDCNT) to issue a PALL
(precharge all banks) command.
5. Use the CMD bits in DBCMDCNT to issue a REF (auto-refresh) command.
6. Set the SRFEN bit in DBRFCNT0 to 1, to make a transition to self-refresh.
7. Check that the SRFEN bit is 1 by reading the SDRAM refresh control register (DBRFCNT0).
8. Use a general-purpose port or other means to convey to the external device that the SDRAM
has entered the self-refresh state. Upon receiving this notification, the external device should
change the MBKPRST signal from high level to low level.
9. Turn off the unnecessary power, other than the DBSC2 1.8 V I/O.
(2) Recovery from SDRAM Power Supply Backup Mode
The following method is used.
1. Turn on the power supply to the LSI.
2. Input a power-on reset to the LSI.
3. After release of power-on reset, an external device should change the MBKPRST signal from
low to high level.
4. An external control circuit decides, using a general-use port or the like, whether to perform a
normal initialization sequence of the SDRAM, or to recover from power supply backup mode.
For normal initialization sequence of the SDRAM, refer to section 12.5.3, Initialization
Sequence.
Rev.1.00 Jan. 10, 2008 Page 548 of 1658
REJ09B0261-0100