SH7785 Datasheet, PDF (1516/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29. User Break Controller (UBC)
⎯ If the post-instruction-execution break and data access break have occurred simultaneously
with the re-execution type exception (including the pre-instruction-execution break) having
a higher priority, only the re-execution type exception is accepted, and no condition match
flags are set. When the exception handling has finished thus clearing the exception source,
and when the same instruction has been executed again, the break occurs setting the
corresponding flag.
⎯ If the post-instruction-execution break or operand access break has occurred
simultaneously with the completion-type exception (TRAPA) having a higher priority, then
no user break occurs; however, the condition match flag is set.
6. When conditions have been satisfied simultaneously and independently for channels 0 and 1,
resulting in identical SPC values for both of the breaks, the user break occurs only once.
However, the condition match flags are set for both channels. For example,
Instruction at address 110 (post-instruction-execution break for instruction fetch for channel 0)
→ SPC = 112, CCMFR.MF0 = 1
Instruction at address 112 (pre-instruction-execution break for instruction fetch for channel 1)
→ SPC = 112, CCMFR.MF1 = 1
7. It is not allowed to set the pre-instruction-execution break or the operand break in the delayed
slot instruction of the RTE instruction. And if the data value is included in the match
conditions of the operand break, do not set the break for the preceding the RTE instruction by
one to six instructions.
8. If the re-execution type exception and the post-instruction-execution break are in conflict for
the instruction requiring two or more execution states, then the re-execution type exception
occurs. Here, the CCMFR.MF0 (or CCMFR.MF1) bit may or may not be set to 1 when the
break conditions have been satisfied.
Rev.1.00 Jan. 10, 2008 Page 1486 of 1658
REJ09B0261-0100