SH7785 Datasheet, PDF (1658/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix
B. Mode Pin Settings
The MODE14–MODE0 pin values are input in the event of a power-on reset via the PRESET pin.
Note: The MODE6 pin is output state after power-on reset.
Legend:
H: High level input
L: Low level input
Table B.1 Clock Operating Modes with External Pin Combination
Pin Value
MODE [4:0]
Clock
Pin Number
Operating
Mode
43210
0
LLLLL
OSC/
External
input
Frequency
[MHz]
Frequency
(vs. Input Clock)
Divider PLL
Min Max ¹
1 Ick Uck SHck GAck DUck Pck
12 17 × 1
× 36 × 18 × 18 × 9 × 9 × 3
DDRck Bck
× 18 × 6
1
LLLLH
× 36 × 18 × 18 × 9 × 9 × 3/2 × 18 × 3/2
2
L L L HL
× 36 × 12 × 12 × 6 × 6 × 3 × 12 × 6
3
L L L HH
× 36 × 12 × 12 × 6 × 6 × 3/2 × 12 × 3/2
16
H L L L L 23 34 × 1
× 36 × 18 × 9 × 9 × 9/2 × 9/2 × 3/2 × 9 × 3
17
HL L L H
× 18 × 9 × 9 × 9/2 × 9/2 × 3/4 × 9 × 3/4
18
HL L HL
× 18 × 6 × 6 × 3 × 3 × 3/2 × 6 × 3
19
HL L HH
× 18 × 6 × 6 × 3 × 3 × 3/4 × 6 × 3/4
Note: When MODE12 or MODE11 is set to low level, DUck is stopped.
The division ratio of the divider 2 can be read out from FRQMR1.
For details, see section 15, Clock Pulse Generator (CPG).
Rev.1.00 Jan. 10, 2008 Page 1628 of 1658
REJ09B0261-0100