SH7785 Datasheet, PDF (268/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Caches
8.7 Store Queues
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory.
8.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 8.9. These two store queues
can be set independently.
SQ0 ^{SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]}
SQ1 ^{SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]}
4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte
Figure 8.9 Store Queue Configuration
8.7.2 Writing to SQ
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to
H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of
the address bits are as follows:
[31:26] : 111000
[25:6] : Don't care
[5]
: 0/1
[4:2] : LW specification
[1:0] : 00
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification
1: SQ1 specification
Specifies longword position in SQ0/SQ1
Fixed at 0
Rev.1.00 Jan. 10, 2008 Page 238 of 1658
REJ09B0261-0100