SH7785 Datasheet, PDF (303/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
10.3 Register Descriptions
Table 10.3 shows the INTC register configuration. Table 10.4 shows the register states in each
operating mode.
Table 10.3 INTC Register Configuration
Name
Abbreviation R/W P4 Address
Interrupt control register 0 ICR0
R/W H'FFD0 0000
Interrupt control register 1 ICR1
R/W H'FFD0 001C
Interrupt priority register
Interrupt source register
INTPRI
INTREQ
R/W H'FFD0 0010
R/(W)*¹ H'FFD0 0024
Interrupt mask register 0
INTMSK0
R/W H'FFD0 0044
Interrupt mask register 1
INTMSK1
R/W H'FFD0 0048
Interrupt mask register 2
INTMSK2
R/W H'FFD4 0080
Interrupt mask clear register 0 INTMSKCLR0 R/W H'FFD0 0064
Interrupt mask clear register 1 INTMSKCLR1 R/W H'FFD0 0068
Interrupt mask clear register 2 INTMSKCLR2 R/W H'FFD4 0084
NMI flag control register
NMIFCR
R/(W)*² H'FFD0 00C0
User interrupt mask level
register
USERIMASK R/W H'FFD3 0000
Interrupt priority registers
INT2PRI0
R/W H'FFD4 0000
INT2PRI1
R/W H'FFD4 0004
INT2PRI2
R/W H'FFD4 0008
INT2PRI3
R/W H'FFD4 000C
INT2PRI4
R/W H'FFD4 0010
INT2PRI5
R/W H'FFD4 0014
INT2PRI6
R/W H'FFD4 0018
INT2PRI7
R/W H'FFD4 001C
INT2PRI8
R/W H'FFD4 0020
INT2PRI9
R/W H'FFD4 0024
Interrupt source register (not INT2A0
affected by the mask state)
R
H'FFD4 0030
Access Sync.
Area 7 Address Size Clock
H'1FD0 0000 32
Pck
H'1FD0 001C 32
Pck
H'1FD0 0010 32
Pck
H'1FD0 0024 32
Pck
H'1FD0 0044 32
Pck
H'1FD0 0048 32
Pck
H'1FD4 0080 32
Pck
H'1FD0 0064 32
Pck
H'1FD0 0068 32
Pck
H'1FD4 0084 32
Pck
H'1FD0 00C0 32
Pck
H'1FD3 0000
32
Pck
H'1FD4 0000 32
Pck
H'1FD4 0004 32
Pck
H'1FD4 0008 32
Pck
H'1FD4 000C 32
Pck
H'1FD4 0010 32
Pck
H'1FD4 0014 32
Pck
H'1FD4 0018 32
Pck
H'1FD4 001C 32
Pck
H'1FD4 0020 32
Pck
H'1FD4 0024 32
Pck
H'1FD4 0030 32
Pck
Rev.1.00 Jan. 10, 2008 Page 273 of 1658
REJ09B0261-0100