SH7785 Datasheet, PDF (640/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
2
MAIM
0
SH: R/WC Master-Abort Interrupt Mask
PCI: R
0: MAI disabled (masked)
1: MAI enabled (not masked)
1
RDPEIM 0
SH: R/WC Read Data Parity Error Interrupt Mask
PCI: R
0: RDPEI disabled (masked)
1: RDPEI enabled (not masked)
0
WDPEIM 0
SH: R/WC Write Data Parity Error Interrupt Mask
PCI: R
0: WDPEI disabled (masked)
1: WDPEI enabled (not masked)
(12) PCI Arbiter Bus Master Information Register (PCIBMIR)
In host mode, this register records when the interrupt is generated by PCIAINT. When multiple
interrupts occur, only the first source is registered. When an interrupt is disabled, the source is
registered in the corresponding bit, and no interrupt occurs.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
REQ3 REQ2 REQ1 REQ0 PCIC
BME BME BME BME BME
Initial value: 0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Rev.1.00 Jan. 10, 2008 Page 610 of 1658
REJ09B0261-0100