SH7785 Datasheet, PDF (646/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
1
PMD1M 0
SH: R/W PCI Power Management D1 Status Transition
PCI: ⎯ ^{Interrupt Mask}
0: PMD1 disabled (masked)
1: PMD1 enabled (not masked)
0
PMD0M 0
SH: R/W PCI Power Management D0 Status Transition
PCI: ⎯ ^{Interrupt Mask}
0: PMD0 disabled (masked)
1: PMD0 enabled (not masked)
(16) PCI Memory Bank Register 0 (PCIMBR0)
This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory
read or write to the PCI memory space 0 by the CPU or DMAC.
See section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PMSBA0
——
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Initial
Bit
Bit Name Value R/W
31 to 18 PMSBA0 H'0000 SH: R/W
PCI: ⎯
17 to 0 ⎯
All 0 SH: R
PCI: ⎯
Description
PCI Memory Space 0 Bank Address (14 bits)
These bits specify an bank address for the PCI
memory space 0 for PIO transfer.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 616 of 1658
REJ09B0261-0100