SH7785 Datasheet, PDF (1225/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
24.3.9 Transfer Byte Number Count Register (TBCR)
TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred
(block size) for each single block transfer command. TBCR specifies the number of data block
bytes not including the start bit, end bit, and CRC.
The multiple block transfer command corresponds to the number of bytes of each data block. This
setting is ignored by the stream transfer command.
Bit: 7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ _{C3 C2 C1 C0}
Initial value: 0
R/W: R
0
0
RR
0
0
0
0
0
R R/W R/W R/W R/W
Bit
7 to 4
3
2
1
0
Bit Name
—
CS3
CS2
CS1
CS0
Initial
Value R/W
All 0 R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Data Block Size
Four or more bytes should be set before executing a
command with data transfer.
0000: 1 byte (for forced erase)
0001: 2 bytes
0010: 4 bytes
0011: 8 bytes
0100: 16 bytes
0101: 32 bytes
0110: 64 bytes
0111: 128 bytes
1000: 256 bytes
1001: 512 bytes
1010: 1024 bytes
1011: 2048 bytes
1100 to 1111: Setting prohibited
Rev.1.00 Jan. 10, 2008 Page 1195 of 1658
REJ09B0261-0100