SH7785 Datasheet, PDF (254/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Caches
8.3.3 Write Operation
When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is written to a cacheable
area, the cache operates as follows:
1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual
address bits [12:5].
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
from virtual address translation by the MMU:
⎯ If there is a way whose tag matches and its V bit is 1, see No. 3 for copy-back and No. 4
for write-through.
⎯ I If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
selected to replace using the LRU bits is 0, see No. 5 for copy-back and No. 7 for write-
through.
⎯ If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
selected to replace using the LRU bits is 1, see No. 6 for copy-back and No. 7 for write-
through.
3. Cache hit (copy-back)
A data write in accordance with the access size is performed for the data field on the hit way
which is indexed by virtual address bits [4:0]. Then 1 is written to the U bit. The LRU bits are
updated to indicate the way is the latest one.
4. Cache hit (write-through)
A data write in accordance with the access size is performed for the data field on the hit way
which is indexed by virtual address bits [4:0]. A write is also performed to external memory
corresponding to the virtual address. Then the LRU bits are updated to indicate the way is the
latest one. In this case, the U bit isn't updated.
5. Cache miss (copy-back, no write-back)
A data write in accordance with the access size is performed for the data field on the hit way
which is indexed by virtual address bits [4:0]. Then, the data, excluding the cache-missed data
which is written already, is read into the cache line on the way which is selected to replace
from the physical address space corresponding to the virtual address.
Data reading is performed, using the wraparound method, in order from the quad-word data (8
bytes) including the cache-missed data. While the remaining data on the cache line is being
read, the CPU can execute the next processing. When reading of one line of data is completed,
the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit
and the U bit on the way. Then the LRU bit is updated to indicate the way is latest one.
Rev.1.00 Jan. 10, 2008 Page 224 of 1658
REJ09B0261-0100