SH7785 Datasheet, PDF (1618/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8
CLKOUT
t_FMD
RD/FRAME
t_FMD
D31 to D0
t_WDD t_WDD t_RDS
t_RDH
A
D1 D2 D3 D4 D5 D6 D7 D8
CSn
t_CSD
t_CSD
RD/WR
RDY
t_RWD
t_RDYS
t_RDYH
t_RWD
t_BSD t_BSD
BS
DACKn
(DA)
t_DACD
t_DACD
(1) 1st data: One internal wait cycle, 2nd to 8th data: No waitl
Information in the first data bus cycle
D31 to D29: Access size
000:
Byte
001:
Word (2 bytes)
010:
Longword (4 bytes)
011:
Quadword (8 bytes)
1xx:
Burst (32 bytes)
D25 to D0: Address
Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3
Tmd7 Tmd8w Tmd8
CLKOUT
RD/FRAME
D31 to D0
CSn
RD/WR
RDY
BS
DACKn
(DA)
t_FMD
t_WDD
A
t_CSD
t_WDD t_RDS
t_RDH
D1
t_RWD
t_RDYS
t_RDYH
t_BSD t_BSD
t_DACD
t_FMD
D3 D4
D6
D8
t_CSD
t_RDYS
t_RDYH
t_RWD
t_DACD
(2) 1st data: No internal wait, 2nd to 8th data: No internal wait + external wait control
Information in the first data bus cycle
D31 to D29: Access size
000:
Byte
001:
Word (2 bytes)
010:
Longword (4 bytes)
011:
Quadword (8 bytes)
1xx:
Burst (32 bytes)
D25 to D0: Address
Legend:
IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
Figure 32.22 MPX Bus Cycle (Burst Read)
Rev.1.00 Jan. 10, 2008 Page 1588 of 1658
REJ09B0261-0100