SH7785 Datasheet, PDF (475/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CLKOUT
A25 to A0
CSn
R/W
RD
D31 to D0
(In reading)
WEn
11. Local Bus State Controller (LBSC)
T1
Tw
Twe
T2
BS
RDY
DACKn
In this example, DACKn is active-high.
Figure 11.40 Wait State Timing of Byte Control SRAM
(One Internal Wait + One External Wait)
Rev.1.00 Jan. 10, 2008 Page 445 of 1658
REJ09B0261-0100