SH7785 Datasheet, PDF (620/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
13.3.3 PCI Local Registers
(1) PCI Control Register (PCICR)
PCICR is a 32-bit register which controls the operation of the PCIC in this LSI.
Writing to this register is valid only when the value of bits 31 to 24 are H'A5.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
— PFCS FTO PFE TBS — BMAM —
—
—
IOCS
RST
CTL
CFINT
Initial value: 0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0
SH R/W: R R R R R/W R/W R/W R/W R R/W R R R R/W R/W R/W
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 24 ⎯
Initial
Value
H'00
23 to 12 ⎯
All 0
11
PFCS
0
R/W
Description
SH: R/W Reserved
PCI: R These bits should be set to H'A5 (write H'A5 to these
bits) only before bits 11 to 8, 6, and 2 to 0 are written.
These bits are always read as 0.
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
SH: R/W PCI Pre-Fetch Command Setting
PCI: R
Specifies the access size for pre-fetch when the target
memory read access is issued by an external PCI
device.
This bit is valid only when the PFE bit is 1.
0: 8-byte pre-fetch is always performed
1: 32-byte pre-fetch is always performed
Rev.1.00 Jan. 10, 2008 Page 590 of 1658
REJ09B0261-0100