SH7785 Datasheet, PDF (441/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
CLKOUT
A25-A0
CSn
R/W
TAS1 T1 TS1 Tw Tw Tw Tw T2 TH1 TH2 TAH1
RD
*¹
D31-D0
TS1: CSn assertion - RD assertion delay cycle
CSnWCR RDS = 001
TH1, TH2: RD negation - CSn negation delay cycle
CSnWCR RDH = 010
TAS1: Address setup wait
CSnWCR ADS=001
Tw: Access wait
CSnWCR IW = 0100
TAH1: Address hold wait
CSnWCR AHS = 001
WEn
D31-D0
(ADS=000)
CLKOUT
CLKOUT
D31-D0
(ADS=001 to 111)
TS1: CSn assertion - WEn assertion delay cycle
CSnWCR WTS = 001
TH1, TH2: WE negation - CSn negation delay cycle
CSnWCR WTH = 010
TAS1: Address setup wait
CSnWCR BSH=001
Tw: Access wait
CSnWCR IW = 0100
TAH1: Address hold wait
CSnWCR ADH = 001
BS
*²
Notes: 1. When CSnBCR RDSPL is set to 1
2. When CSnWCR BSH is set to 1
Figure 11.11 SRAM Interface Wait Timing (Read-Strobe/Write-Strobe Timing Setting)
Rev.1.00 Jan. 10, 2008 Page 411 of 1658
REJ09B0261-0100