SH7785 Datasheet, PDF (1487/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29. User Break Controller (UBC)
29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for
channels 0 and 1, respectively. The following break conditions can be set in the CBR0 and CBR1:
(1) whether or not to include the match flag in the conditions, (2) whether or not to include the
ASID, and the ASID value when included, (3) whether or not to include the data value, (4)
operand size, (5) whether or not to include the execution count, (6) bus type, (7) instruction fetch
cycle or operand access cycle, and (8) read or write access cycle.
• CBR0
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFE AIE
MFI
AIV
Initial value : 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
SZ
Initial value : 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R R R
876543210
CD
ID
RW
CE
000000000
R R/W R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31
MFE
0
R/W Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1, the
condition is determined to be satisfied.
0: The match flag is not included in the match conditions;
thus, not checked.
1: The match flag is included in the match conditions.
30
AIE
0
R/W ASID Enable
Specifies whether or not to include the ASID specified by
the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
thus, not checked.
1: The ASID is included in the match conditions.
Rev.1.00 Jan. 10, 2008 Page 1457 of 1658
REJ09B0261-0100