SH7785 Datasheet, PDF (564/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
MCK0,
MCK1
MCKE
High level
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
Valid
MA[10]
Valid
Invalid
Invalid
Valid Invalid Valid
Valid Invalid Valid
MBA[2:0] Valid Invalid Valid Invalid Valid
Invalid
Invalid
Invalid
Example of CL = 3
MDQS[3:0]
MDM[3:0]
Invalid
Invalid
MDQ[31:0]
SDRAM _ACT
command _{bank A}
Invalid
WRITE
bank A
WRITE
bank A
Write data
Invalid
Figure 12.11 Waveforms for 32-Byte Writing (When the Bus Width Is Set to 32 Bits)
Figure 12.12 shows waveforms during auto-refresh operation resulting from settings of the
SDRAM refresh control registers 0, 1, and 2. The DBSC2 issues a REF command automatically
after the PALL command is issued when at least one DDR2-SDRAM bank is activated before the
REF command. Consequently, there is no need to use software to manage precharging of all the
banks for the auto-refresh operation.
Rev.1.00 Jan. 10, 2008 Page 534 of 1658
REJ09B0261-0100