SH7785 Datasheet, PDF (1005/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
Table 20.2 GDTA Register Configuration (CL Block)
Name
Abbreviation R/W
CL command FIFO
CLCF
W
CL control register
CLCR
R/W
CL status register
CLSR
R
CL frame width setting CLWR
R/W
register
CL frame height setting CLHR
R/W
register
CL input Y padding size CLIYPR
R/W
setting register
CL input UV padding CLIUVPR
R/W
size setting register
CL output padding size CLOPR
R/W
setting register
CL palette pointer setting CLPLPR
R/W
register
Area 7
P4 Address Address
Access Sync
Size Clock
H'FE40 1000 H'1E40 1000 32
GAck
H'FE40 1004 H'1E40 1004 32
GAck
H'FE40 1008 H'1E40 1008 32
GAck
H'FE40 100C H'1E40 100C 32
GAck
H'FE40 1010 H'1E40 1010 32
GAck
H'FE40 1014 H'1E40 1014 32
GAck
H'FE40 1018 H'1E40 1018 32
GAck
H'FE40 101C H'1E40 101C 32
GAck
H'FE40 1020 H'1E40 1020 32
GAck
Rev.1.00 Jan. 10, 2008 Page 975 of 1658
REJ09B0261-0100