SH7785 Datasheet, PDF (1648/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
32.3.17 FLCTL Module Signal Timing
Table 32.22 NAND-Type Flash Memory Interface Timing
Item
Symbol Min.
Max.
Command issue setup time
t_NCDS
Command issue hold time
t
NCDH
Data output setup time
t_NDOS
Data output hold time
t_NDOH
Command to address transition time 1 t
NCDAD1
Command to address transition time 2 t_NCDAD2
FWE cycle time
t
NWC
FWE low pulse width
t
NWP
2 × t_fcyc −10 —
1.5 × t −10 —
fcyc
0.5 t_fcyc −10 —
0.5 t_fcyc −10 —
1.5 × t −10 —
fcyc
2 × t_fcyc −10 —
t −5
—
fcyc
0.5 t −5 —
fcyc
FWE high pulse width
Address to ready/busy transition time
Ready/busy to data read transition
time 1
t
NWH
t_NADRB
t_NRBDR1
0.5 t −5
fcyc
—
1.5 × t_fcyc
—
32 × t_pcyc
—
Ready/busy to data read transition t
32 × t
—
NRBDR2
pcyc
time 2
FSC cycle time
FSC high pulse width
FSC low pulse width
Read data setup time
Read data hold time
Data write setup time
Command to status read transition
time
t
NSCC
t
NSPH
t
NSP
t
NRDS
t_NRDH
t_NDWS
t_NCDSR
t
—
fcyc
0.5 × t −5 —
fcyc
0.5 × t −5 —
fcyc
24
—
5
—
32 × t_pcyc −10 —
4 × t_fcyc −10 —
Command output off to status read t_NCDFSR
3.5 × t_fcyc
—
transition time
Status read setup time
t
NSTS
2.5 × t −10
fcyc
Notes: 1. t_pcyc is the period of one peripheral clock (Pck) cycle.
2. t_fcyc is the period of one FLCTL clock (Fck) cycle.
Unit Figure
ns 32.67, 32.71
ns
ns 32.67, 32.68,
ns ^{32.70, 32.71}
ns 32.67, 32.68
ns 32.68
ns 32.68, 32.70
ns 32.67, 32.68,
32.70, 32.71
ns 32.68, 32.70
ns 32.68, 32.69
ns 32.69
ns
ns
ns
ns 32.69, 32.71
ns
ns
ns 32.70
ns 32.71
ns
ns
Rev.1.00 Jan. 10, 2008 Page 1618 of 1658
REJ09B0261-0100