SH7785 Datasheet, PDF (1020/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.12 CL Command FIFO (CLCF)
CLCF is in the CL register block and receives commands. This register uses the FIFO method and
recognizes four command parameters according to the writing order. This register does not retain
the written values. This register is always read as 0.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL_CF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CL_CF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name
Value R/W Description
31 to 0 CL_CF
0
W Command FIFO register
Notes: 1. Setting Method
When accessing this register, the CL_EN bit in GACER should be set to 1. Access is
possible only when the CL_EN bit is set to 1. If the CL_EN bit is 0, access is invalid
(writing is invalid; the result of reading is indefinite).
The following shows the parameter contents assumed according to the writing order:
Writing Order
CL command parameter 1
CL command parameter 2
CL command parameter 3
CL command parameter 4
Setting Contents
Input Y pointer
Input U pointer
Input V pointer
Output pointer
CL command
• Input Y pointer: Pointer for input Y data (Input Y data storing address)
• Input U pointer: Pointer for input U data (Input U data storing address)
• Input V pointer: Pointer for input V data (Input V data storing address)
• Output pointer: Pointer for output data (Output data storing address)
Rev.1.00 Jan. 10, 2008 Page 990 of 1658
REJ09B0261-0100