SH7785 Datasheet, PDF (229/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
7.8 32-Bit Address Extended Mode
Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29-
bit physical address space to 32-bit address extended mode which handles the 32-bit physical
address space.
Virtual address space
U0/P0
(2 Gbytes)
29-bits
address space
0.5 Gbyte
Virtual address space
U0/P0
(2 Gbytes)
32-bit
address space
P1 (0.5 Gbyte)
P2 (0.5 Gbyte)
P3 (0.5 Gbyte)
P4 (0.5 Gbyte)
29-bit Physical address space
(Normal mode)
P1/P2
(1 Gbyte)
P3 (0.5 Gbyte)
P4 (0.5 Gbyte)
4 Gbytes
32-bit Physical address space
(Extended mode)
Figure 7.26 Physical Address Space (32-Bit Address Extended Mode)
7.8.1 Overview of 32-Bit Address Extended Mode
In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The
PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode
to the 32-bit physical address space. In areas which are target for address translation of the TLB
(UTLB/ITLB), upper three bits in the PPN field of the UTLB or ITLB are extended and then
addresses after the TLB translation can handle the 32-bit physical addresses.
As for the cache operation, P1 area is cacheable and P2 area is non-cacheable in the case of 29-bit
address mode, but the cache operation of both P1 and P2 area are determined by the C bit and WT
bit in the PMB in the case of 32-bit address mode.
Rev.1.00 Jan. 10, 2008 Page 199 of 1658
REJ09B0261-0100