SH7785 Datasheet, PDF (340/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(4) Interrupt Mask Register (INT2MSKR)
INT2MSKR is a 32-bit readable/writable register that can mask interrupts for sources indicated in
the interrupt source register. When a bit in this register is set to 1, the interrupt in the
corresponding bit is not notified. INT2MSKR is initialized to H'FFFF FFFF (all masked) by a
reset.
After this register is written to or the masking is cleared by writing to INT2MSKCLR, the timing
required to reflect the register value is guaranteed by reading from this register once.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 10.9 shows the correspondence between bits in INT2MSKR and the interrupts that are
masked.
Table 10.9 Correspondence between Bits in INT2MSKR and Interrupts that Are Masked
Initial
Bit Value R/W Source
Function
Description
31 to All 1
29
28 1
27 1
26 1
25 1
24 1
23 1
22 1
R Reserved
These bits are always read as 1. Masks interrupt of each
The write value should always be 1. on-chip peripheral
R/W GDTA
Masks GDTA interrupt
module
R/W DU
Masks DU interrupt
R/W SSI channel 1 Masks the SSI channel 1 interrupt
R/W SSI channel 0 Masks the SSI channel 0 interrupt
[When written]
0: Invalid
1: Interrupt is masked
[When read]
R/W GPIO
Masks the GPIO interrupt
0: Not masked
R/W FLCTL
Masks the FLCTL interrupt
1: Masked
R/W MMCIF
Masks the MMCIF interrupt
21 1
R/W HSPI
Masks the HSPI interrupt
20 1
R/W SIOF
Masks the SIOF interrupt
19 1
R/W PCIC (5)
Masks PCIERR and PCIPWD3 to
PCIPWD0 interrupt
Rev.1.00 Jan. 10, 2008 Page 310 of 1658
REJ09B0261-0100