SH7785 Datasheet, PDF (1363/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

(2) Reception Using Interrupt Data Flow Control
26. Serial Sound Interface (SSI) Module
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable data interrupt,
enable error interrupts
Wait for interrupt from SSI
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
SSI
Yes
Error interrupt?
No
Read data from
receive data register
Use SSI status register bits
to realign data
after underflow/overflow
Yes
More data to be
received?
No
Disable SSI module,
disable data interrupt
disable error IRQ,
enable idle IRQ
Wait for idle interrupt
from SSI module
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
End
Figure 26.24 Reception Using Interrupt Data Flow Control
Rev.1.00 Jan. 10, 2008 Page 1333 of 1658
REJ09B0261-0100