SH7785 Datasheet, PDF (1000/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
Figure 20.1 shows the GDTA block diagram.
External memory
(external)
LBSC
CPU
SuperHyway bus
DDR2IF
DDR2-SDRAM
(external)
GDTA
Target interface
Response
queue
(4 planes)
Request
queue
(4 planes)
Control
register
Initiator interface
Arbiter
CLW-
CLR-
MCW-
MCR-
GADMAC GADMAC GADMAC GADMAC
Buffer RAM
interface
CL/MC
interface
Color conversion
table control
IDCT control
RAM 0 interface
arbiter
RAM 1 interface
arbiter
Buffer
RAM 0
(8 Kbytes)
CL
function block
MC
function block
Buffer
RAM 1
(8 Kbytes)
Figure 20.1 GDTA Block Diagram
Rev.1.00 Jan. 10, 2008 Page 970 of 1658
REJ09B0261-0100