SH7785 Datasheet, PDF (651/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(21) PCI Memory Bank Mask Register 2 (PCIMBMR2)
This register is the mask register for PCIMBR2. This register specifies the memory space size on
the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC.
See section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———
MSBAM2
——
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit
Bit Name
31 to 29 ⎯
Initial
Value
All 0
R/W
SH: R
PCI: ⎯
28 to 18 MSBAM2 All 0
SH: R/W
PCI: ⎯
17 to 0 ⎯
All 0 SH: R
PCI: ⎯
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Memory Space 2 Bank Address Mask (11 bits)
0 0000 0000 00: 256 kbytes
0 0000 0000 01: 512 kbytes
0 0000 0000 11: 1 Mbyte
0 0000 0001 11: 2 Mbytes
0 0000 0011 11: 4 Mbytes
0 0000 0111 11: 8 Mbytes
0 0000 1111 11: 16 Mbytes
0 0001 1111 11: 32 Mbytes
0 0011 1111 11: 64 Mbytes
0 0111 1111 11: 128 Mbytes
0 1111 1111 11: 256 Mbytes
1 1111 1111 11: 512 Mbytes
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 621 of 1658
REJ09B0261-0100