SH7785 Datasheet, PDF (1006/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
Table 20.3 GDTA Register Configuration (MC Block)
Name
Abbreviation R/W
MC command FIFO
MCCF
W
MC status register
MCSR
R
MC frame width setting MCWR
R/W
register
MC frame height setting MCHR
R/W
register
MC Y padding size
MCYPR
R/W
setting register
MC UV padding size MCUVPR
R/W
setting register
MC output frame Y
pointer register
MCOYPR
R/W
MC output frame U
pointer register
MCOUPR
R/W
MC output frame V
pointer register
MCOVPR
R/W
MC past frame Y pointer MCPYPR
R/W
register
MC past frame U pointer MCPUPR
R/W
register
MC past frame V pointer MCPVPR
R/W
register
MC future frame Y
pointer register
MCFYPR
R/W
MC future frame U
pointer register
MCFUPR
R/W
MC future frame V
pointer register
MCFVPR
R/W
P4 Address
H'FE40 2000
H'FE40 2004
H'FE40 2008
Area 7
Address
H'1E40 2000
H'1E40 2004
H'1E40 2008
Access Sync
Size Clock
32
GAck
32
GAck
32
GAck
H'FE40 200C H'1E40 200C 32
GAck
H'FE40 2010 H'1E40 2010 32
GAck
H'FE40 2014 H'1E40 2014 32
GAck
H'FE40 2018 H'1E40 2018 32
GAck
H'FE40 201C H'1E40 201C 32
GAck
H'FE40 2020 H'1E40 2020 32
GAck
H'FE40 2024 H'1E40 2024 32
GAck
H'FE40 2028 H'1E40 2028 32
GAck
H'FE40 202C H'1E40 202C 32
GAck
H'FE40 2030 H'1E40 2030 32
GAck
H'FE40 2034 H'1E40 2034 32
GAck
H'FE40 2038 H'1E40 2038 32
GAck
Rev.1.00 Jan. 10, 2008 Page 976 of 1658
REJ09B0261-0100