SH7785 Datasheet, PDF (809/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.5.3 Manual Reset by Watchdog Timer Overflow
The time period taken by manual reset on watchdog timer overflow (WDT manual reset holding
time) is equal to or more than 30 cycles of the peripheral clock (Pck).
The transition time from watchdog timer overflow to the manual reset state (WDT reset setup
time) is equal to or more than eight cycles of the peripheral clock (Pck).
(1) Manual Reset Caused by Watchdog Timer Overflow during Normal Operation
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
EXTAL
input
CLKOUT
output
CLKOUTENB
output
WDT overflow
signal
MRESETOUT
output
STATUS[1:0]
output
LL (normal)
HH (reset)
LL (normal)
WDT reset setup time
WDT manual reset holding time
Figure 16.8 STATUS Output by Manual Reset Caused by WDT Overflow
during Normal Operation
Rev.1.00 Jan. 10, 2008 Page 779 of 1658
REJ09B0261-0100