SH7785 Datasheet, PDF (273/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 On-Chip Memory
9. On-Chip Memory
This LSI includes three types of memory modules for storage of instructions and data: OL
memory, IL memory, and U memory. The OL memory is suitable for data storage while the IL
memory is suitable for instruction storage. The U memory can store instructions and/or data.
9.1 Features
(1) OL Memory
• Capacity
The OL memory in this LSI is 16 Kbytes.
• Page
The OL memory is divided into four pages (pages 0A, 0B, 1A and 1B).
• Memory map
The OL memory is allocated in the addresses shown in table 9.1 in both the virtual address
space and the physical address space.
Table 9.1 OL memory Addresses
Page 0A
Page 0B
Page 1A
Page 1B
H'E500 E000 to H'E500 EFFF
H'E500 F000 to H'E500 FFFF
H'E501 0000 to H'E501 0FFF
H'E501 1000 to H'E501 1FFF
• Ports
Each page has three independent read/write ports and is connected to the SuperHyway bus, the
cache/RAM internal bus, and operand bus. The operand bus is used when the OL memory is
accessed through operand access. The cache/RAM internal bus is used when the OL memory
is accessed through instruction fetch. The SuperHyway bus is used for OL memory access
from the SuperHyway bus master module.
• Priority
In the event of simultaneous accesses to the same page from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
Cache/RAM internal bus > operand bus.
Rev.1.00 Jan. 10, 2008 Page 243 of 1658
REJ09B0261-0100