SH7785 Datasheet, PDF (642/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(13) PCI PIO Address Register (PCIPAR)
Setting this register generates configuration cycles on the PCI bus. For details, see section 13.4.5
(2), Configuration Space Access.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCIE — — — — — — —
BN
Initial value: 1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
SH R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DN
FN
CRA
——
Initial value: x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Initial
Bit
Bit Name Value
31
CCIE
1
30 to 24 ⎯
All 0
23 to 16 BN
H'xx
R/W Description
SH: R
PCI: ⎯
Configuration Cycle Issue Enable
0: Indicates that configuration cycle issue is disable
1: ⎯
SH: R Reserved
PCI: ⎯ These bits are always read as 0. The write value
should always be 0.
SH: R/W PCI Bus Number
PCI: ⎯
These bits specify a PCI bus number for the
configuration access target. The bus number 0
indicates the bus to which the PCIC is connected. A
bus number is represented by an 8-bit value in the
range from 0 to 255.
Rev.1.00 Jan. 10, 2008 Page 612 of 1658
REJ09B0261-0100